1. Field of the Invention
The present invention relates to a digital clock generator circuit for producing a modified clock signal which is synchronized with a sync signal having a time-base variation from a fixed, stable clock signal, and to a video signal time-base error corrector apparatus using the digital clock generator circuit.
2. Description of the Prior Art
A time-base error corrector (referred to as a TBC hereinafter) is used for compensating for a time base error attributed to a playback signal reproduced from a recording medium, e.g. a disk or tape. A digital TBC requires a modified clock signal synchronized with a sync signal of the playback signal.
In the prior art, the modified clock signal synchronized with a sync signal is generated by a PLL (phase locked loop) circuit. However, a loop filter and a VCO (voltage controlled oscillator) which are primary components of the PLL are commonly operable in an analog state, thus requiring delicate adjustment for desirable performance and suffering from interference with noise derived from an adjacent digital circuit to result in an unstable operation. To overcome such drawbacks, the PLL may be adapted for complete digital operation. In this case, when the digital PLL is required to operate at a high speed, its amount of arithmetical operation and bit rate will substantially increased so as to be too high to be practically implemented.
The digital PLL may be replaced by a digital phase synchronizing circuit as disclosed in Japanese Laid-open Patent Publication No. 62-110382(1989) wherein clock signals at the write and read sides of a RAM (random access memory) in a time-base error corrector are controlled separately. The clock signal control at the write side is executed by causing each reproduced sync signal to be in phase with a reference clock signal. The clock signal control at the read side is effected by detecting the duration of the reproduced sync clock signal, and producing a difference between the duration of the reproduced clock signal and the duration of the reference sync signal as a velocity error signal, and calculating a clock control amount through a polynomial operation of a previous series of the velocity error signals for phase modulation of the clock signal. In such a time-base error corrector, since a time base error is corrected by phase control on the clock signal at the read side of the RAM, a time-base error corrected signal will be obtained only in the analog state after D/A (digital-to-analog) conversion. In other words, such a prior art time-base error corrector cannot be digital interfaced with other digital devices. Also, the polynomial operation using a plurality of velocity error signals requires a continuous series of reproduced sync signals. Generally, a playback signal from a recording medium tends to have dropouts, and the absence of one of the series of the reproduced sync signals will cause consumption of a considerable length of time before the polynomial operation produces a correct value.